GradNova

Vlsi, Asynchronous Circuit Design and Architecture, Timing Analysis, and Formal Verification

1 faculty research Vlsi, Asynchronous Circuit Design and Architecture, Timing Analysis, and Formal Verification on GradNova.

K

Professor

Department of Electrical and Computer Engineering

University of Utah

Vlsi, Asynchronous Circuit Design and Architecture, Timing Analysis, and Formal Verification

Low-Power High-Performance VLSI Design

Parallel Computing and Optimization Techniques

Embedded Systems Design Techniques

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